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Chandra Sekhar, P.
- Hardware Implementation of High Performance AES Using Minimal Resources
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Authors
Affiliations
1 Dept. of Electronics & Communication Engg., RGMCET, Nandyal, Kurnool (Dist), IN
1 Dept. of Electronics & Communication Engg., RGMCET, Nandyal, Kurnool (Dist), IN
Source
International Journal of Engineering Research, Vol 3, No SP 2 (2014), Pagination: 68-72Abstract
Increasing need of data protection in computer networks led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. Hardware implementation of cryptographic algorithms are physically secure than software implementations since outside attackers cannot modify them. In order to achieve higher performance in today's heavily loaded communication networks, hardware implementation is a wise choice in terms of better speed and reliability. This paper presents the hardware implementation of Advanced Encryption Standard (AES) algorithm using Xilinx-virtex5 Field Programmable Gate Array (FPGA). In order to achieve higher speed and lesser area, Sub Byte operation, Inverse Sub Byte operation, Mix Column operation and Inverse Mix Column operations are designed as Look Up Tables (LUTs) and Read Only Memories (ROMs). This approach gives a throughput of 3.74Gbps utilizing only 1% of total slices in xc5vlx110t-3-ff1136 target device.Keywords
AES, Rijndael, Cryptography, FPGA, Verilog, Encryption, Decryption.- Three Stage Scheduling of Steel Making Using Earliest Deadline First Algorithm
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Authors
Affiliations
1 IT Department, Visakhapatnam Steel Plant, RINL, A.P, IN
2 Department of CS, Andhra Univrsity, Vizag, A.P, IN
3 Department of CSE, Adikavi Nannaya University, A.P, IN
4 Department of Metallurgy, Andhra University, A.P, IN
1 IT Department, Visakhapatnam Steel Plant, RINL, A.P, IN
2 Department of CS, Andhra Univrsity, Vizag, A.P, IN
3 Department of CSE, Adikavi Nannaya University, A.P, IN
4 Department of Metallurgy, Andhra University, A.P, IN